View CDP1879_92778.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CDP1879, CDP1879C-1
March 1997
CMOS Real-Time Clock
Description
The CDP1879 real-time clock supplies time and calendar information from seconds to months in BCD format. It consists of 5 separately addressable and programmable counters that divide down an oscillator input. The clock input can have any one of 4 possible frequencies, allowing flexibility in the choice of crystal or external clock sources. Using an external 32kHz clock source, timekeeping can be performed down to 2.5V (see Standby (Timekeeping) Voltage Operation). The device can be memory-mapped for use with any general-purpose microprocessor and has the additional capability of operating in the CDP1800 series input/output mode. The real-time clock functions as a time-of-day/calendar with an alarm capability that can be set for combinations of seconds, minutes or hours. Alarm time is configured by loading alarm latches that activate an interrupt output through a comparator when the counter and alarm latch values are equal. Fifteen selectable square-wave signals are available as a separate clock output signal and can also activate the interrupt output. A status register is available to indicate the interrupt source. The value in an 8 bit control register determines the operational characteristics of the device, by selecting the prescaler divisor and the clock output, and controls the load and alarm functions. A transparent "freeze" circuit preclude clock rollover during counter and latch access times to assure stable and accurate values in the counters and alarm latches. The CDP1879 is functionally identical to the CDP1879C-1. The CDP1879 has a recommended operating voltage range of 4V to 10.5V, and the CDP1879C-1 has a recommended operating voltage range of 4V to 6.5V. The CDP1879 and the CDP1879C-1 are supplied in 24 lead hermetic dual-in-line side-brazed ceramic packages (D suffix) and 24 lead dual-in-line plastic packages (E suffix).
Features
* CPU Interface for Use with General-Purpose Microprocessors * Time Of Day/Calendar * Reads Seconds, Minutes, Hours * Reads Day of Month and Month * Alarm Circuit With Seconds, Minutes or Hours Operation * Power Down Mode * Separate Clock Output Selects 1 of 15 Square Wave Signals * Interrupt Output Activated By Clock Output and/or Alarm Circuit * Date Integrity Sampling for Clock Rollover Eliminated * On-Board Oscillator: - Crystal Operation CDP1879 at 10V . . . . . . . 4.19MHz, 2.09MHz or 1.048MHz - Crystal Operation CDP1879C-1 at 5V . . . . . 4.19MHz, 2.09MHz or 1.048MHz or 32kHz - External Clock Operation at 10V or 5V. . . . 4.19MHz, 2.09MHz, 1.048MHz or 32kHz * Addressable in Memory Space or CDP1800 Series I/O Mode * Low Standby (Timekeeping) Voltage with External Clock * Related Literature - AN7275, Guide to the Use of CD1879 and CDP1879C1 Real Time Clock
Ordering Information
PACKAGE TEMP RANGE -40oC to +85oC -40oC to +85oC 5V CDP1879CE1 CDP1879CD1 CDP1879CD1X 10V CDP1879E PKG. NO. E24.6 D24.6 D24.6
Pinout
CDP1879, CDP1879C-1 (PDIP, SBDIP) TOP VIEW
INT RESET POWER DOWN RD IO/MEM TPB/WR TPA CS A2 1 2 3 4 5 6 7 8 9 24 VDD 23 XTAL 22 XTAL 21 CLK OUT 20 DB7 19 DB6 18 DB5 17 DB4 16 DB3 15 DB2 14 DB1 13 DB0
PDIP SBDIP Burn-In
CDP1879 Modes of Operation
OPERATION
Read Write
FUNCTION
1. Seconds, minutes, hours, date and month counters 2. Status register to identify interrupt source 1. Control register to set device operation 2. Seconds, minutes, hours, date and month counters 3. Alarm latches for alarm time 1. Three-state interrupt output with active alarm or clock out circuitry for wake-up control 2. Data bus and address inputs are "DON'T CARE" 1. Clock out as source 2. Alarm time as source 3. Either interrupt can occur during normal or power down mode
Power Down
A1 10 A0 11 VSS 12
Interrupt
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1360.2
4-104
CDP1879, CDP1879C-1
Absolute Maximum Ratings
DC Supply Voltage Range, VDD (Voltage referenced to VSS Terminal) CDP1879 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1879C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5 to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . 10mA Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . . 40mW For TA = Full Package Temperature Range (All Package Types)
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 50 12 Operating Temperature Range (TA) Package Type D, H . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 in. (1.59 0.79mm) From Case for 10s Max
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions at TA = FuIl Package-Temperature Range, Unless Otherwise specified. For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges: LIMITS CDP1879 PARAMETER DC Operating Voltage Range Input Voltage Range DC Standby (Timekeeping) Voltage (Note 1), TA = -40oC to +85oC (Note 2) TA = 0o to +70oC Clock Input Rise or Fall Time, VDD = 5V VDD = 10V NOTES: 1. Timekeeping function only, no READ/WRITE accesses, 32kHz external frequency source only, no crystal operation. 2. See Standby (Timekeeping) Voltage Operation. tR, tF 10 1 10 s s VSTBY 3 2.5 3 2.5 V V MIN 4 VSS MAX 10.5 VDD CDPl879C-1 MIN 4 VSS MAX 6.5 VDD UNITS V V
4-105
CDP1879, CDP1879C-1
FREEZE CIRCUIT AM - PM AND HOUR LOGIC CALENDAR LOGIC
XTAL XTAL OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY MONTH
PRESCALE SELECT
CLOCK SELECT
CLOCK OUT INT RESET VDD VSS CLOCK AND INT. LOGIC
CONTROL REGISTER
8-BIT DATA BUS
COMPARATOR SECOND LATCH MINUTE LATCH HOUR LATCH
INT. STATUS REGISTER
DB0-DB7 A0 A1 A2 TPA I-O MEM TPB/WR RD CS POWER DOWN
I/O INTERFACE
ADDRESS DECODE AND CONTROL LOGIC
FIGURE 1. REAL-TIME CLOCK FUNCTIONAL DIAGRAM TABLE 1. CONTROL REGISTER BIT ASSIGNMENT Bit 1, 0 Frequency 00 Select 01 10 11 Bit 2 Start/Stop 32768Hz 1.048576MHz 2.097152MHz 4.194304MHz 1 = Start 0 = Stop ADDRESSES Latch, Counter Seconds Latch, Counter Minutes Latch, Counter Hours Counter, Day Counter, Month Control, Register Status Register TABLE 2. A2 0 0 1 1 1 1 1 A1 1 1 0 0 1 1 1 A0 0 1 0 1 0 1 1
Bit 3 Counter/Latch Control "0" = Write to Counter and disable alarm "1" = Write to and enable alarm Clock Select Bit 7, 6, 5, 4 0000 - disables 0001 - 488.2s 0010 - 976.5s 0011 - 1953.1s 0100 - 3906.2s 0101 - 7812.5s 0110 - 15.625ms 0111 - 31.25ms 1000 - 62.5ms 1001 - 125ms 1010 - 250ms 1011 - 500ms 1100 - sec. 1101 - min. 1110 - hour 1111 - day
MSB of Hours Counters (Bit 7) is an AM-PM Bit. 0 = AM; 1 = PM Bit 6 of Hours Counter Controls 12/24 hr. 1 = 12 Hr: 0 = 24 Hr. Status Register: Bit 7 MSB = Alarm Interrupt Source: Bit 6 = Clock. MSB of Month Counter (Bit 7) is a Leap Year Bit 0 = No, 1 = Yes.
4-106
CDP1879, CDP1879C-1
Static Electrical Specifications at TA -40oC to +85oC VDD 5%, Unless Otherwise Specified
CONDITIONS CDP1879 PARAMETER Ouiescent Device Current IDD 0.4 0.5 4.6 9.5 0.4 lOL 0.5 4.6 9.5 0.4 lOL 0.5 4.6 9.5 VOL VOH VIL VIH IIN 0.5, 4.5 0.5, 9.5 0.5, 4.5 0.5, 9.5 Any Input 0, 5 IOUT 0,10 VO (V) VIN (V) 0, 5 0, 10 Output Low Drive (Sink) Current, Data Bus and INT lOL Output High Drive (Source) Current, Data Bus and INT IOH Output Low Drive (Sink) Current, Clock Out 0, 5 0,10 0, 5 0,10 0, 5 0,10 0, 5 0,10 0, 5 0,10 0, 5 0,10 0, 5 0,10 0, 5 0, 10 0, 5 0, 10 0,5 0,10 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 MIN 1.8 3.6 -1.1 -2.6 0.6 1.2 -1.1 -2.6 0.2 0.4 -0.15 -0.3 4.9 9.9 3.5 7 (NOTE 1) TYP 0.01 1 4 7 -2.3 -4.4 1.4 3 -2.3 -4.4 0.9 2 -0.4 -0.7 0 0 5 10 MAX 50 200 0.1 0.1 1.5 3 1 2 1 1 0.15 1 1.5 2 0.25 2 3 4.5 0.25 0.5 0.6 0.8 3 3.5 5 MIN -1.1 0.6 -1.1 0.2 -0.15 4.9 3.5 LIMITS CDPl879C-1 (NOTE 1) TYP 0.02 -2.3 1.4 -2.3 0.9 -0.4 0 5 MAX 200 0.1 1.5 1 1 V mA UNITS A
Output High Drive (Source) Current, Clock Out IOH Output Low Drive (Sink) Current, XTAL Out
Output High Drive (Source) Current, XTAL Out IOH Output Voltage Low-Level (Note 2) Output Voltage High Level (Note 2) Input Low Voltage Input High Voltage Input Leakage Current Three-State Output Leakage Current Operating Current (Note 3) External Clock External Clock External Clock External Clock External Clock External Clock External Clock External Clock XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) XTAL Oscillator (Note 4) 32kHz 1MHz 2MHz 4MHz 32kHz 1MHz 2MHz 4MHz 32kHz 1MHz 2MHz 4MHz 1MHz 2MHz 4MHz
A
-
-
5 5 5 5 10 10 10 10 5 5 5 5 10 10 10
-
0.01 0.2 0.35 0.7 0.03 0.4 0.8 1.6 0.1 0.3 0.4 0.6 1.6 1.8 2
-
0.01 0.2 0.35 0.7 0.1 0.3 0.4 0.6 -
0.15 1 1.5 2 mA 0.25 0.5 0.6 0.8 -
4-107
CDP1879, CDP1879C-1
Static Electrical Specifications at TA -40oC to +85oC VDD 5%, Unless Otherwise Specified
CONDITIONS CDP1879 PARAMETER Input Capacitance Output Capacitance Maximum Clock Rise and Fall Times NOTES: 1. Typical values are for TA = 25oC and nominal VDD. 2. IOL = IOH = 1A. 3. Operating current measured with clockout = 488.2s and no load. 4. See Table 3 and Figure 6 for oscillator circuit information. CIN COUT tR, tF VO (V) VIN (V) VDD (V) 5 10 MIN (NOTE 1) TYP 5 10 MAX 7.5 15 10 1 MIN LIMITS CDPl879C-1 (NOTE 1) TYP 5 10 MAX 7.5 15 10 s UNITS pF (Continued)
Programming Model
WRITE AND READ REGISTERS
BCD FORMAT DB7 TENS 0-5 SECONDS COUNTER (00-59) DB7 TENS 0-5 MINUTES COUNTER (00-59) TENS 0-5 DB7 X DB6 X TENS 0-2 UNITS 0-9 DB0 SECONDS ALARM LATCH (00-59) DB7 TENS 0-5 MINUTES ALARM LATCH (00-59) DB7 TENS 0-3 DAY OF MONTH COUNTER (01-28, 29, 30, 31) DB7 X TENS 0 OR 1 UNITS 0-9 DB0 UNITS 0-9 X X TENS 0-2 UNITS 0-9 DB0 DB7 DB6 DB0 UNITS 0-9 DB0 UNITS 0-9 UNITS 0-9 DB7 DB0 DB0 UNITS 0-9 CONTROL REGISTER DB0-DB1 - FREQUENCY SELECT DB2 - START/STOP DB3 - COUNTER/ALARM LATCH CONTROL DB4-DB7 - CLOCK OUTPUT SELECT DB7 DB0 7 6 5 4 3 2 1 0
WRITE ONLY REGISTERS
DB0
HOURS COUNTER (01 - 12 OR 00-23) DB7 0=AM, 1=PM DB6 0=24 HR, 1=12 HR
HOURS ALARM LATCH (01-12 OR 00-23 12 HR, DB7=0 AM, 1=PM 24 HR, DB7=X
READ ONLY REGISTER
DB7 X DB6 X 0 0 0 0 0 DB0 0
MONTH COUNTER (JAN=1 DEC=12) DB7 0=NO LEAP YEAR 1=LEAP YEAR
INTERRUPT STATUS REGISTER DB7=1 ALARM CIRCUIT ACTIVATED INT. DB6=1 CLOCK OUTPUT ACTIVATED INT.
4-108
CDP1879, CDP1879C-1
REGISTER TRUTH TABLE ADDRESS A2 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 A1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 AO 0 0 1 1 0 0 1 1 0 0 0 1 0 1 1 ACTIVE SIGNAL TPB/WR X X X X X X X X X RD X X X X X X BIT 3 CONTROL REGISTER 0 0 0 0 0 0 0 0 0 0 1 1 1 REGISTER OPERATION Write Seconds Counter Read Seconds Counter Write Minutes Counter Read Minutes Counter Write Hours Counter Read Hours Counter Write Date Counter Read Date Counter Write Month Counter Read Month Counter Write Seconds Alarm Latch Write Minutes Alarm Latch Write Hours Alarm Latch Write Control Register Read Int. Status Register
General Operation
The real-time clock contains seconds, minutes, and hours, date and month counters that hold time of day/calendar information (see Figure 2). The frequency of an intrinsic oscillator is divided down to supply a once-a-second signal to the counter series string. The counters are separately addressable and can be written to or read from. The real-time clock contains seconds, minutes and hour write-only alarm latches that store the alarm time (see Figure 3). When the value of the alarm latches and counters are equal, the interrupt output is activated. The interrupt output can also be activated by a clock output transition. The clock output is derived from the prescaler and counters and can be one of 15 square-wave signals. The value in the readonly interrupt status register identifies the interrupt source. Operational control of the real-time clock is determined by the byte in a write-only control register. The 8-bit value in this register determines the correct divisor for the prescaler, a data direction and alarm enable bit, clock output select, and start/stop control (see Figure 4). Data transfer and addressing are accomplished in two modes of operation, memory mapping and I/O mapping using the CDP1800-series microprocessors. The mode is selected by the level on an input pin. (IO/MEM). Memory mapping implies use of the address lines as chip selects and address inputs during linear selection or partial or full decoding methods. I/O mapping with the CDP1800-series microprocessors involves use of the N line outputs in conjunction with input and output instructions to transfer data to and from memory.
4-109
CDP1879, CDP1879C-1
FREEZE CIRCUIT
AM - PM AND HOUR LOGIC
CALENDAR LOGIC
XTAL XTAL OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY MONTH
PRESCALE SELECT
CLOCK SELECT
CLOCK OUT INT RESET VDD VSS CLOCK AND INT. LOGIC
CONTROL REGISTER
8-BIT DATA BUS
COMPARATOR SECOND LATCH MINUTE LATCH HOUR LATCH
INT. STATUS REGISTER
DB0-DB7 A0 A1 A2 TPA IO/MEM TPB/WR RD CS POWER DOWN
I/O INTERFACE
ADDRESS DECODE AND CONTROL LOGIC
FIGURE 2. FUNCTIONAL DIAGRAM - TIME COUNTERS HIGHLIGHTED
4-110
CDP1879, CDP1879C-1
AM - PM AND HOUR LOGIC
FREEZE CIRCUIT
CALENDAR LOGIC
XTAL XTAL OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY MONTH
PRESCALE SELECT
CLOCK SELECT
CLOCK OUT INT RESET VDD VSS CLOCK AND INT. LOGIC
CONTROL REGISTER
8-BIT DATA BUS
COMPARATOR SECOND LATCH MINUTE LATCH HOUR LATCH
INT. STATUS REGISTER
DB0-DB7 A0 A1 A2 TPA IO/MEM TPB/WR RD CS POWER DOWN
I/O INTERFACE
ADDRESS DECODE AND CONTROL LOGIC
FIGURE 3. FUNCTIONAL DIAGRAM - ALARM CIRCUIT, CLOCK OUTPUT, INTERRUPT, AND STATUS REGISTERS HIGHLIGHTED
Operational Sequence
Power is applied and the real-time clock is reset. This sets the interrupt output pin high. After the CS pin is set high and with address 7 on the address input lines, the control register is loaded via the data bus to configure the clock. With selective addressing, the seconds through month counters are then written to and loaded to set the current time. The real-time clock will now hold the current "wall clock" time, with an accuracy determined by the crystal or external clock used. If the alarm function is desired, the control register is accessed and loaded again. This new byte will allow subsequent time data to be entered into the seconds, minutes and hours alarm latches. This sequence is also used when selecting one of the 15 available clock-out signals. If the alarm function was selected, the interrupt output pin will be set low when the values in the seconds, minutes and hour alarm latches match those in the seconds, minutes and hour counters. If one of the 15 sub second-to-day clock outputs is selected by the byte in the control register, the clock output pin toggles at that frequency (50% duty cycle) The interrupt output will also be set low on the first clock out negative transition. The interrupt source (alarm or clock out) can be determined by reading the interrupt status register. The clock output can be deselected by placing zero in the upper nibble of the control register if the alarm function is selected as the only interrupt source.
Counters
The counter section consists of an on-board oscillator, a prescaler and 5 counters that hold the time of day/calendar information (see Figure 2). 1 of 4 possible external crystals determine the frequency of the on-board oscillator (32,768Hz, 1.048576MHz, 2.097152MHz, 4.194304MHz). The oscillator output is divided down by a pres-
4-111
CDP1879, CDP1879C-1
caler that supplies a once-a-second pulse to the counters. The seconds counter divide the pulse by 60 and its output clocks the minute counter every 60 seconds Further division by the minutes, hours, day of month and month counters result in 5 counters holding data that reflect the time/calendar from seconds to months. The counters are addressed separately and BCD data is transferred to and from via the data bus. The most significant bit of the hours counter (Bit 7) is user programmed to
FREEZE CIRCUIT
indicate AM or PM and will be inverted every 12th hour. (0=AM, 1=PM). Bit 6 of the hours counter is user programmed to enable the hours counter for 12 or 24 hour operation. (0=24,1=12). If 24-hour operation is selected, the AM-PM bit is "don't care", but still toggles every 12th hour. Writing to the seconds counter resets the last 7 stages of the prescaler, allowing time accuracy to approximately 1/100 of a second.
AM - PM AND HOUR LOGIC
CALENDAR LOGIC
XTAL XTAL OSCILLATOR PRESCALE SECOND MINUTE HOUR DAY MONTH
PRESCALE SELECT
CLOCK SELECT
CLOCK OUT INT RESET VDD VSS CLOCK AND INT. LOGIC
CONTROL REGISTER
8-BIT DATA BUS
COMPARATOR SECOND LATCH MINUTE LATCH HOUR LATCH
INT. STATUS REGISTER
DB0-DB7 A0 A1 A2 TPA IO/MEM TPB/WR RD CS POWER DOWN
I/O INTERFACE
ADDRESS DECODE AND CONTROL LOGIC
FIGURE 4. FUNCTIONAL DIAGRAM - CONTROL REGISTER HIGHLIGHTED
The most significant bit of the month counter is a Leap Year bit. If it is set to "1", the counter will count to February 29, then roll to March 1. If set to "0" it will go to March 1st after February 28th.
Alarm And Interrupt Status Register
The alarm circuit consists of 1) seconds, minutes and hour alarm latches that hold the alarm time, 2) the outputs of the seconds, minutes and hour counters, and 3) a comparator that drives an interrupt output. The comparator senses the counter and alarm latch values and activates the interrupt output (active low) when they are equal (see Figure 3).
The write-only alarm latches have the same addresses as their comparable counters. Bit 3 in the control register determines data direction to the latches or counters and alarm enabling. For example, during a write cycle, if bit-3 in the control register is a "1", addressing the seconds counter or alarm latch will load the seconds alarm latch from the data bus and will enable the alarm function. Conversely, if bit-3 in the control register is a "0", addressing the seconds counter or alarm latch during a write cycle will place the value on the data bus into the seconds counter and will disable the alarm function. The interrupt output can be activated by the alarm circuit or the clock output. When an interrupt occurs, the
4-112
CDP1879, CDP1879C-1
upper two bits of the interrupt status register identify the interrupt source. The interrupt status register has the same address as the control register. Addressing the interrupt status register with the RD line active will place these register bits on the data bus. Bits 0-5 are held low. A "1" in bit-6 represents a clock output transition as the interrupt source. A "1" in bit-7 will identify the alarm circuit as the interrupt source. Activating the reset pin (active low) resets the hour latch to "30" which prevents a match between alarm and time registers during an initialization procedure. Activating the reset pin or writing to the control register resets the interrupt output (high) and clears the interrupt status register 1) A "0" in bit-3 will direct subsequent data to or from the counter selected and the alarm function will be disabled. 2) A "1" in bit-3 will direct subsequent data to or from the alarm latch and will enable the alarm. 4. Bits 4 to 7 - Clock Select - These bits select one of 15 square-wave signals that will be present at the "clockout" pin. If bit-4 to bit-7 are zero's, the clock output pin will be high. If a clock is selected, the first high-to-low clock out transition will activate the interrupt pin (active low) and place a "1" in bit-6 of the status register. Writing to the control register or activating the reset pin will set the interrupt pin high and reset the interrupt status register. Normal operation requires the control register to be written to and loaded first with a control word. However, subsequent writing to a counter if a "clock out" is selected may cause an interrupt out signal. Therefore, "clock-out" should be deselected by writing zero's into bit-4 through bit-7 if the interrupt is used. When the counters are loaded, the control register is again written to with the value in the upper nibble selecting the "clock out" signal. See Table 1.
Clock Output
One of 15 counter and prescaler overflows can be selected as a 50% duty cycle output signal that is available at the "clock out" pin. The frequency is selected by the upper nibble in the control register. For example, selecting a one-second clock output will result in a repetitive signal that will be high for 500ms and low for the same period. The high-to-low transition of the output signal will set the clock bit in the status register and activate the interrupt output. The level of the "clock out" signal is derived from the value in the counter. Example - if hours clock is selected and the minutes counter holds 4 minutes, the clock out will be low for 26 minutes and high for 30 minutes Thereafter, the clock out will toggle at a 50% duty cycle rate (see Table 1 and Figure 3).
CONTROL REGISTER (SEE TABLE 1 AND FIGURE 4) BIT 7 6 5 4 3 2 1 BIT 0
Read And Write Signals
When the IO/MEM pin is low, the real-time clock is enabled for memory mapped operation. Data on the bus is placed in, or read from a counter, alarm latch or register by 1) placing the CS pin high, 2) selective addressing, 3) placing the TPB/WR pin low during a write cycle with the RD pin high or 4) setting the RD pin low during a read cycle with this TPB/WR pin high. The I/O mapping mode used with the CDP1800 series microprocessor is selected by setting the IO/MEM pin high. The TPB/WR pin on the real-time clock is connected to the TPB output pin of the microprocessor. Data on that bus is written to or read from the counters, latches and registers by 1) placing the CS pin high, 2) selective addressing utilizing the microprocessor N lines and I/O instructions, 3) placing the TPB/WR pin high with the RD pin low during an output or write operation (data is latched on TPB's trailing edge), 4) setting the RD line high during an input or read operation. Data is placed on the bus by the real-time clock between the trailing edges of TPA and TPB.
CONTROL REGISTER BYTE
The 8-bit value in the control register determines the following: 1. Bit 0 and 1 - Frequency Select - Since there are one of 4 possible crystals the oscillator in the real-time clock can operate with, these bit levels determine the prescaler divisor so that an accurate one second pulse is supplied to the counter series string.
BIT 1 0 0 1 1 BIT 0 0 1 0 1 FREQUENCY 32,768Hz 1.048576MHz 2.097152MHz 4.194304MHz
Freeze Circuit
Since writing to or reading from the counters or alarm latches is performed asynchronously, the once-a-second signal from the prescaler may pulse the counter series string during these operations. This can result in erroneous data. To avoid this occurring, a transparent "freeze" circuit' is incorporated into the real-time clock. This circuit is designed to trap and hold the one-second input clock transition if it occurs during access times. When the operations are completed, it is inserted into the counter series string. To utilize the "freeze" circuit, address "1" (A0 = 1, A1 = 0, A2 = 0) is selected first while performing a write operation. Read or write accesses may now be performed with assurance the data is stable. All operations must be concluded within
2. Bit 2 - Start-Stop Control - Counter enabling is controlled by the value at this location. A "1" will allow the counters to function and a "0" in this location will disable the counters. 3 Bit 3 - Counter/Latch Control - The level at this location controls two functions. It is required since the counters and alarm latches have the same addresses.
4-113
CDP1879, CDP1879C-1
250ms of the address "1" access. In memory mapping any dummy write operation after selecting address "1" will set the "freeze" circuit. If using the I/O mode, a 61 output instruction will perform the same function. There is no time restriction on subsequent accesses as long as the read or write operations are preceded by selecting address "1". Microprocessor Real-Time Clock
MRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RD TPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPB/WR TPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPA N LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDRESS LINES
Power Down
Power down operation is initiated with a low signal on the "POWER DOWN" input pin. In conjunction with the interrupt output, it is used to supply external control circuits with a 3 level control signal. The operating current is not appreciably reduced during "POWER DOWN" operation. When power down is initiated, any inputs on the address or data bus are ignored. The clock output is set low. The interrupt output is three-stated. If enabled previously, the alarm circuitry is active and will set the interrupt output pin low when alarm time occurs. The interrupt output will also go low if a clock was selected and an internal high-to-low transition occurs during power down. The clock output pin will remain low. If power down is initiated in the middle of a read or write sequence, it will not become activated until the read or write cycle is completed.
IO/MEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
CS - CHIP SELECT - Used to enable or disable the inputs and outputs. TPA is used to strobe and latch a positive level on this pin to enable the device. XTAL AND XTAL - The frequency of the internal oscillator is determined by the value of the crystal connected to these pins. "XTAL" may be driven directly by an external frequency source. Clock Out - 1 of 15 square wave frequencies will appear at this pin when selected. During power down, this pin will be placed low, and will be high during normal operation when the clock is deselected. Power Down - Power Down Control - A low on this pin will place the device in the power down mode. INT - Interrupt Output - A low on this pin indicates an active alarm time or high-to-low transition of the "clock out" signal. RESET - A low on this pin clears the status register and places the interrupt output pin high.
Pin Functions
VDD, VSS - Power and ground for device. DB0 - DB7 - DATA BUS - 8-bit bidirectional bus that transfers BCD data to and from the counters, latches and registers. A0, A1, A2 - Address inputs that select a counter, latch or register to read from or write to. TPA - Strobe input used to latch the value on the chip select pin. CS is latched on the trailing edge of TPA. During memory mapping, it is used to latch the high order address bit used for the chip select. When the real-time clock is used with other microprocessors, or when the high order address of the CDP1800 series microprocessor is externally latched, it is connected to VDD . In the input/output mode, it is used to gate the N lines. IO/MEM - Tied low during memory mapping and high when the input/output mode of the CDP1800 series microprocessor is used. RD, TPB/WR - Direction Signals - Active signals that determine data direction flow. In the memory mapped mode, data is placed on the bus from the counters or status register when RD pin is active. Data is transferred to a counter, latch or the control register when RD is high and TPB/WR is active and latched on the trailing edge (low to high) of the TPB/WR signal. In the input/output mode, data is placed on the bus from a counter or status register when RD is not active between the trailing edges of TPA and TPB. Data on the bus is written to a counter, latch, or the control register during TPB when RD is active and latched on TPB's trailing edge. The following connections are required between the microprocessor and realtime clock in the CDP1800 series I/O mode.
Frequency Input Requirements
The Real-Time Clock operates with the following frequency input sources: 1. An external crystal that is used with the on-board oscillator. The oscillator is biased by a large feedback resistor and oscillates at the crystal frequency (see Figure 6, Table 3). 2. An external frequency input that is supplied at the XTAL input. XTAL is left open (see Figure 5). A typical external oscillator circuit is shown in Figure 7 in section, "Standby (Timekeeping) Voltage Operation".
4-114
CDP1879, CDP1879C-1
TABLE 3. TYPICAL OSCILLATOR CIRCUIT PARAMETERS FOR SUGGESTED OSCILLATOR CIRCUIT, SEE FIGURE 6 PARAMETER RF C0 C1 RS CL Crystal Impedance NOTE: CDP1879C-1 only. 4.197MHz 22 39 5 73 2.097MHz 22 39 5 200 1.049MHz 22 39 5 200 32768Hz (NOTE) 22 39 5 200 91 50K (max.) UNITS M pF pF k pF
Design Considerations for Stable Crystal Oscillation 1. Stray capacitances should be minimized for best oscillator performance. Circuit board traces should be kept to a maximum of 1 inch, and there should be no parallel traces. 2. A signal line or power source line must not cross or go near the oscillator circuit line. 3. It is advisable to put a 0.1F capacitor between VDD and VSS of the CDP1879.
CDP1879 XTAL PIN 23 EXTERNAL FREQUENCY SOURCE XTAL CL CDP1879 XTAL PIN 23 PARALLEL RESONANT CRYSTAL
RF PIN 22 RS
CO
CI
FIGURE 6. SUGGESTED OSCILLATOR CIRCUIT APPLIED TO REAL-TIME CLOCK (SEE TABLE 3)
Standby (Timekeeping) Voltage Operation
When any one of the four specified crystals is used with the on-board oscillator, the Real-Time Clock can operate at a minimum of 4V VDD . However, at 32kHz the clock will run (timekeeping only, no device READ/WRITE accesses) down to 3V at -40oC to +85oC and 2.5V at 0o to +70oC. To achieve this low voltage operation, an external 32kHz clock source must be supplied at the XTAL input (see Figure 7). The standby requirements for CHIP SELECT/DESELECT are listed in Table 4, and Figure 8 indicates the timing waveforms. Figure 9 illustrates the typical timekeeping curve over the full temperature range.
PIN 22 XTAL
FIGURE 5. CONNECTIONS FOR AN EXTERNAL FREQUENCY SOURCE APPLIED TO REAL-TIME CLOCK
+3V 14 22 MEG. RF 2 22 3 4 1 24 23
200K 5PF 39PF RL
1/3 CD54/74HC04
CDP1879
FIGURE 7. TYPICAL EXTERNAL CLOCK-SOURCE CIRCUIT
4-115
CDP1879, CDP1879C-1
STANDBY (TIMEKEEPING) CHARACTERISTICS AT FULL TEMPERATURE RANGE LIMITS CDP1879 PARAMETER Chip Deselect to Standby (Timekeeping) Voltage Time Recovery to Normal Operation Time tCSTBY tRC VDD (V) 5 10 5 10 VSTBY (V) 2.5, 3 2.5, 3 2.5, 3 2.5, 3 MIN 2 1 2 1 MAX CDP1879C-1 MIN 2 2 MAX UNITS
s
EXTERNAL CLOCK SOURCE OF 32kHz TYPICAL STANDBY (TIMEKEEPING) VOLTAGE 3V (-40oC T +85oC) 2.5V (-0oC T +70oC STANDBY (TIMEKEEPING VOLTAGE (V) (VSTBY + VDD) 5
STANDBY VOLTAGE MODE VDD tSTBY CS VIH VIL 0.95 VDD VSTBY 0.95 VDD tF (NOTE 1) tRC VIH VIL
4
3
tR (NOTE 1)
2
1
NOTE: 1. tR, tF 1s FIGURE 8. STANDBY (TIMEKEEPING) VOLTAGE AND TIMING WAVEFORMS
0 -40
-20
0
20
40
60
80
100
FULL TEMPERATURE RANGE - oC
FIGURE 9. TYPICAL STANDBY (TIMEKEEPING) VOLTAGE vs FULL TEMPERATURE RANGE
Applications
A typical application for this real-time clock is as a wake-up control to a CPU to reduce total system power in intermittent-use systems. A hookup diagram illustrating this feature is shown in Figure 10. In this configuration, the alarm and power-down features of the CDP1879 are utilized in the control of the sleep and wake-up states of the CPU. A typical shut-down/start-up sequence for this system could proceed as follows: 1. The CPU has finished a current task and will be inactive for the next six hours. 2. The CPU loads the CDP1879 alarm registers with the desired wake-up time. 3. The CDP1800 Q output is set high, which stops the CPU oscillator (as an alternative, in an NMOS system, power to all components except the clock chip could be shut off). 4. This Q output signal is received by the CDP1879 as a power-down signal. 5. The CDP1879 three-states the interrupt output pin. 6. The CDP1879 eventually times out, and sets an alarm by driving the INT output low. 7. The alarm signal resets the CPU (to avoid oscillator startup problems) and flags the processor for a warm-start routine. 8. The CPU, once into its normal software sequence, writes to the CDP1879 control register to reset the interrupt request.
4-116
CDP1879, CDP1879C-1
N0 N1 N2 XTAL VDD
XTAL XTAL A0 A1 A2 IO/MEM
XTAL CDP1800 VDD Q VDD 1/2 CD40107 CDP1879
PD
1/2 CD40107 VDD
CLEAR
EFI
INT
FIGURE 10. CPU WAKE-UP CIRCUIT USING THE CDP1879 REAL-TIME CLOCK
XTAL CLEAR MWR MRD TPA INTERRUPT MA0 ADDRESS LINES MA1 MA2 MA7 RESET TPB/WR RD TPA INTERRUPT A0 A1 A2 CS
XTAL CLOCK OUT
IO/MEM CDP1879
VSS
MEMORY
CDP1802
DB0 - DB7
DATA BUS
FIGURE 11. TYPICAL CDP1802 MEMORY MAPPED SYSTEM
4-117
CDP1879, CDP1879C-1
TPA
LATCH HIGH-ORDER ADDRESS FOR CS
ADDRESS
HIGH BYTE
LOW BYTE
TPB/WR
DATA LATCHED
DATA FROM CPU TO REAL TIME CLOCK
VALID DATA
FIGURE 12. CDP1800 SERIES MEMORY MAPPED WRITE CYCLE TIMING WAVEFORMS
TPA
ADDRESS
HIGH BYTE
LOW BYTE OUTPUT DRIVERS
RD DATA FROM REAL TIME CLOCK TO CPU
ENABLED
DISABLED
VALID DATA
FIGURE 13. CDP1800 SERIES MEMORY MAPPED READ CYCLE TIMING WAVEFORMS
XTAL CLEAR TPA MRD TPB INTERRUPT N0 ADDRESS LINES N1 N2 RESET TPA RD TPB/WR INTERRUPT A0 A1 A2
XTAL CLOCK OUT
IO/MEM CS MEMORY CDP1802 CDP1879 DB0 - DB7
VDD
FIGURE 14. TYPICAL CDP1802 INPUT/OUTPUT MAPPED SYSTEM
4-118
CDP1879, CDP1879C-1
TPA
RD
N LINES
TPB/WR
DATA LATCHED
DATA FROM MEMORY TO REAL-TIME CLOCK
VALID DATA
FIGURE 15. CDP1800 SERIES INPUT/OUTPUT MAPPING TIMING WAVEFORMS WITH OUTPUT INSTRUCTION
TPA OUTPUT DRIVERS ENABLED
RD OUTPUT DRIVERS DISABLED
TPB/WR
N LINES DATA FROM REAL-TIME CLOCK TO MEMORY
VALID DATA
FIGURE 16. CDP1800 SERIES INPUT/OUTPUT MAPPING TIMING WAVEFORMS WITH INPUT INSTRUCTION
Dynamic Electrical Specifications at TA -40oC to +85oC, Input tR, tF = 10ns, CL = 50pF
LIMITS CDP1879 PARAMETER Read Cycle Times (See Figure 17) Data Access from Address tDA 5 10 Read Pulse Width tRD 5 10 Data Access from Read tDR 5 10 Address Hold after Read tRH 5 10 Output Hold after Read tDH 5 10 Chip Select Setup to TPA tCS 5 10 NOTE: 1. Time required by a limit device to allow for the indicated function. 270 160 0 0 50 40 50 30 400 190 375 170 230 130 270 0 50 50 400 375 ns 230 VDD (V) (NOTE 1) MIN MAX CDP1879C-1 (NOTE 1) MIN MAX UNITS
4-119
CDP1879, CDP1879C-1
TPA tCS tRH
ADDRESS/CHIP SELECT
tRD READ
DATA TO CPU
tDR tDA tDH
FIGURE 17. READ CYCLE TIMING WAVEFORMS
Dynamic Electrical Specifications at TA -40oC to +85oC, Input tR, tF = 10ns, CL = 50 pF
LIMITS CDP1879 PARAMETER Write Cycle Times (See Figure 18) Address Setup to Write Write Pulse Width Data Setup to Write Address Hold after Write Data Hold after Write Chip Select Setup to TPA NOTE: 1. Time required by a limit device to allow for the indicated function. tAS tWR tDS tAH tWH tCS 5 10 5 10 5 10 5 10 5 10 5 10 225 110 150 70 65 30 0 0 150 80 50 30 225 150 65 0 150 50 ns VDD (V) (NOTE 1) MIN MAX CDP1879C-1 (NOTE 1) MIN MAX UNITS
4-120
CDP1879, CDP1879C-1
TPA tCS tAH
ADDRESS/CHIP SELECT
tAS WRITE
tWR
DATA TO REAL-TIME CLOCK
tDS
tWH
FIGURE 18. WRITE CYCLE TIMING WAVEFORM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-121

▲Up To Search▲

Price & Availability of CDP1879

	To Download CDP1879 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .